Technical Field
The present disclosure relates to a layout design system, a semiconductor device using the layout design system, and a fabricating method thereof.
Description of the Related Art
One of the scaling technologies for increasing the density of semiconductor devices utilizes multi-gate transistors in which silicon bodies in a fin or nanowire shape are formed on a substrate, with gates then being formed on surfaces of the silicon bodies.
The use of multi-gate transistors allows for easy scaling, as they include a three-dimensional channel. Furthermore, current control capability can be enhanced without requiring increased gate length for the multi-gate transistors. Additionally, it is possible to effectively suppress short channel effect (SCE) which is the phenomenon that the electric potential of the channel region is influenced by the drain voltage.